The present invention relates to a phase locked loop (called hereinafter "PLL") circuit and, more particularly, to a digital PLL circuit for producing a control signal which is locked in a predetermined phase relationship to an input signal supplied with a variable phase.
A digital PLL circuit employed in a data processing sytem requiring a control signal locked in a predetermined phase relationship to an input signal having a variable and arbitrary phase, includes an oscillator, a variable divider, a phase comparator and a control circuit. The oscillator generates a reference clock signal of a constant frequency higher than the frequency of the input signal. The divider frequency-divides the reference clock signal in accordance with a division ratio to produce the control signal. The comparator compares the phase of the control signal with the phase of the input signal and produces phase difference data representative of a phase difference therebetween. The control circuit controls the division ratio of the divider in response to the phase difference data such that the control signal takes a predetermined phase relationship to the input signal.
The digital PLL circuit is required to control the phase of the control signal in such a manner that a phase error between the input and control signals is in a range of one clock cycle of the reference clock signal with a simplified construction. It is further required to easily change a loop gain of the circuit.